1. Field of the Invention
This invention relates to electronic systems utilizing a clock and more particularly relates to implementing one or more test clock modes.
2. Description of the Related Art
Electronic systems such as computer systems have become ubiquitous. Computer systems typically include one or more processors and a bus to connect each processor to each other, if applicable, to memory, and to various input/output devices. These components of the computer system and other computer system circuitry typically include integrated circuitry which responds to an external clock signal supplied to the processor.
One method of increasing electronic system performance involves increasing the clock frequency at which the electronic system components operate. However, as frequencies increase, it has become difficult to externally supply a clock signal at the operational frequencies of all components due to, for example, electromagnetic emission problems and input circuit reactances. Thus, the external clock frequency is typically multiplied by, for example, 2, 3, or 4 using internal processor circuitry.
In many instances, the maximum operational frequency of an electronic circuit is dictated by critical paths i.e. circuit paths where combinational delays are greater than the time allocated for data transmission at the operational frequency. Critical paths may be identified with a "debug tester" that provides known input data to a processor and compares the processor output data with expected output data. If no errors occur, the processor operational frequency may be increased by increasing the external clock frequency, and the debug test may be repeated until an error in the processor output data occurs. Once the debug tester detects an error, debugging software attempts to identify the critical path among the many paths between the input terminal and output terminal. One clock cycle is generally used to propagate data from one path to the next. Thus, N clock cycles are generally utilized for data to propagate through N paths, where N is an integer. To identify the critical path, the debugging software may manipulate the external clock input signal to slow down the clock frequency during a predetermined cycle of the N clock cycles or stretch predetermined cycles. The particular altered cycle may be repeatedly changed both in identification and characteristically according to well-known algorithms until the output data contains no errors. Once the output data is error free, the critical path associated with the altered clock cycle may be isolated.
However, as device operating frequencies continue to increase, allowing manipulation of the external clock frequency to identify critical paths has become unsuitable for many high operational frequency devices.